Color images displayed on contemporary computer display monitors include so-called "inatural images" of the type produced e.g. by color photography. Encoded data representing elements of such images (e.g. pixels) is often stored in computer systems in "YUV" or "YIQ" format. In YUV format, the code representing an image element defines three attributes of the respective element; a luminance factor (Y) and two color factors: red minus Y (U), and red minus blue (V). YIQ encoding is similar to YUV, but contains I and Q element components that align axially with natural images.
In order to display such data on conventional color monitors used in computers and workstations, data representing individual elements of the source (YUV or YIQ) image must be converted to an RGB format which defines relative red, green and blue luminance attributes (RGB) of directly displayable elements of a corresponding image. Such conversions generally have to be performed in real time coordination with operations of the display monitor, so that the RGB image elements are displayed as they are generated, thereby minimizing buffer storage requirements for the data representing these elements. In a typical YUV to RGB conversion, matrix multiplications are performed on color components of the source data (U and V), and results are logically added to respective luminance components (Y) to produce corresponding RGB data components. These operations effectively form three sums of products yielding functions representing red, green and blue components of an RGB image pixel, in which the product terms are formed by multiplying U and V components of each corresponding source pixel by various predetermined constants and in which the corresponding Y component of each source pixel is a separate added term in each sum.
To achieve speeds required to meet display raster constraints, these multiplication and addition functions usually are performed in a hardwired cascaded adder structure containing a number of adder stages linearly related to the number of 1 valued bits in the fractional parts of the multiplicative constants. This type of arrangement can be constructed efficiently if the values of the constants can be chosen to minimize the number of adder stages required. However, it has the disadvantage that only a single set of constants is effectively "wired" into any implementation, allowing no flexibility for adjusting the constants to accommodate variations in image conditions or display parameters. Furthermore, in many instances, the multiplicative constants cannot be chosen to minimize adder stages.
Therefore, in applications in which multiplicative constants need to be changed from time to time, or where they cannot be chosen to optimize a cascaded adder network, adder network structures hitherto used are either too inflexible or subject to excessive pipelining delays which cannot be tolerated.
The present invention provides an alternative arrangement for performing such conversions more flexibly and generally faster than other known arrangements.